1. Field of the Invention
This invention relates generally to metal fill regions, and more particularly to metal fill regions of a semiconductor chip.
2. Description of Background
In modern semiconductor processes, “fill patterns” are used to ensure a fairly constant terrain and therefore avoid dishing during chemical-mechanical polishing (CMP). For example, if a relatively large region of a circuit contains little or no metal for wiring or power distribution, a layout data program puts metal fill into the region. For digital circuits, the extra capacitance caused by placement of the metal fill in these regions may be acceptable. However, for analog circuits, where every farad of capacitance needs to be accounted for, this is a problem, as too large a capacitance can slow electrical transmission in active wire regions of the circuit. Thus, a metal fill strategy that minimizes dishing while also maintaining capacitance at acceptable levels is desirable.